| 摘要 |
PURPOSE:To prevent data from being erroneously detected when data from CPU lacks by using a flip flop in a circuit detecting data from CPU and outputting data by means of the rise of a write pulse. CONSTITUTION:The flip flop 3 latching data from CPU 1 by the rise of the write pulse 7 and a means setting the flip flop 3 by the output of an address decoder 2 are provided. When a designated address is shown by the address bus of CPU 1, data from CPU 1 is outputted at the time of the rise of the write pulse 7, and data is released when the address bus of CPU 1 shows the address except for the designated address. Thus, data is prevented from being erroneously detected. |
