Vertical deflection circuit for high resolution TV receiver - uses storage of vertical deflection current data supplied in synchronism with vertical synchronisation signal

摘要

The vertical deflection circuit has a microprocessor control unit (1) using a stored vertical deflection programme, allowing transmitted deflection current data received from a setting bus (BUS1) to be fed to a data bus (DB2). The data is transmitteed in synchronism with the vertical synchronisation signal (VS). The vertical deflection programme uses four successive stages to allow the transfer of the stored vertical deflection current data to be repeated when the setting bus (BUS1) is not available. ADVANTAGE - Ensures good image stability and linearily.