Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays.

摘要

A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell is disclosed thereafter. A storage element (SE) is comprised of four cross coupled FETs (Q1 to Q4). A fifth FET (Q5) is mounted in a transmission gate configuration between the bit line (BL) and a first common node (A) of the storage element. Its gate electrode is connected to the word line (WL). This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET (Q6) is also mounted in a transmission gate configuration between the second common mode (B) of the storage element and an output line (OL). Its gate electrode is connected to the input (IL). Said second FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at said second common node and on said input line. Other configurations of said sixth FET (Q6) are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs). In the latter case, in the AND array the input and output lines are respectively the product term lines (if bit partitioning is employed) and AND term lines (or Match Lines). In the OR array, the input and output lines are respectively the Match Out lines (the signal on the Match Line after complementation) and the OR out lines. RPLAs can be dynamically reprogrammed to allow in system logical reconfiguration in real time.