| 摘要 |
<p>A VLSI compatible, random number generator being highly invulnerable to cryptographic attack is based upon a low frequency sampling of the output of a pseudo-random number generator which is operated at a varying frequency from a free-running ring oscillator. In a first embodiment, a free-running ring oscillator is used to drive a sampled linear feedback shift register. Because of the variations in power supply voltage and other circuit parameters over time, the frequency produced by the ring oscillator, when applied as the clocking input to the linear feedback shift register, causes the linear feedback shift register to operate in an aperiodic manner. The asynchronous, serial pseudo-random number output from the linear feedback shift register is sampled periodically, thereby introducing randomly occurring deviations from the pseudo-random number sequence. In a second embodiment of the invention, a variation of the free-running ring oscillator is employed as the pseudo-random number generator, by introducing into the feedback loop of the ring oscillator, an exclusive OR circuit which is connected so that the ring oscillator thereby produces a serial, pseudo-random number sequence. Additional uncertainty in the sequence of random numbers produced by the free-running pseudorandom number generator, is caused by the race condition which occurs at the inputs to the exclusive OR connected in the circuit. This can cause unpredictable skipping from a first portion of the pseudo-random number sequence to a second portion of the sequence when unbalanced signal delays occur due to variations in power supply voltage.</p> |
