Data processor with controlled clock pulse generator - has registering circuit and comparator allowing access to be controlled by external codeword signal

摘要

The input data (48) to the data processing unit (10) are fed via a clock generator (20) which incorporates a PLL. The input (48) and output (46) data lines are fed via a register circuit (42) to a comparator (44). The external reference signal input (22) is fed to another circuit (34) where it is compared with output of the other comparator (44). The comparator output (38) is used to control the internal oscillator (30). The oscillator output, which is the system clock, feeds a clock pulse counter (40) together with feedback from the comparator (44). The clock pulse counter (40) provides the other input to the comparator (44). The system can be programmed by an external signal (22) or preset by PROMs or by 'burn-out' links. @(7pp Dwg.No.1/1)@.