| 摘要 |
PURPOSE:To lessen the marginal limitation for step tears in signal wiring and eliminate the need for preparing an alignment slippage margin in order to form source and drain regions and then, make the size of a semiconductor chip small by forming a gate part and power source wiring with the same manufacturing process and forming source and drain regions after injecting impurities by using the above gate part as well as power source wiring as each mask. CONSTITUTION:After forming an N-type region 8 on a P-type semiconductor substrate, a gate insulating film 7 is formed on the whole main surface of the substrate and the gate insulating film 7 at a part of regions 2 for taking off well is removed. Ion implantation is performed so that the foregoing regions 2 are connected electrically to the substrate and N<+> type regions 2 for taking off well are formed. After that, for example, molybdenum as a conductor having a high melting point is deposited on the whole face and a conductor layer 4a having the high melting point is formed. By the use of this layer as a mask, boron ion implantation is performed and P-type source and drain regions 5 are formed. Subsequently, separated parts 3 are removed by a selecting etching technique and a gate electrode terminal 1a and VDD wiring 4 are formed after being separated respectively. Consequently, the source and drain regions are easily formed and the formation of these regions makes the size of a chip small. |
