| 摘要 |
A process of fabricating a semiconductor integrated circuit device, wherein a semiconductor wafer having a number of isolated active areas has a gate insulator layer located within each active area and defining regions to form source and drain regions, respectively, and a gate electrode layer formed on the gate insulator layer, and wherein dopant ions are injected into the source- and drain-forming regions in two steps consisting of a first step of injecting dopant ions in a first direction inclined through a predetermined angle from normal to the surface of the wafer, the first direction having on a plane parallel with the surface of the wafer a projective component angled to the direction of length of the gate electrode layer, the dopant ions being injected into the source- and drain-forming regions with a dose equal to one-half of the total dose required for the formation of the source and drain regions, and a second step of injecting dopant ions in a second direction inclined through the predetermined angle from normal to the surface of the wafer, the second direction having on the plane parallel with the surface of the wafer a projective component angled to the direction of length of the gate electrode layer and diametrically opposite to the projective component of the first direction, the dopant ions being injected into the source- and drain-forming regions with a dose equal to the remaining half of the required total dose.
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