| 摘要 |
<p>PURPOSE:To increase the range of fast and variable speed by providing a clock generation circuit, a pulse generation circuit, and a shift register, sending data in parallel, and changing word length by selecting the number of steps of the shift register. CONSTITUTION:Step change-over switches 2 and 7 are positioned at terminals a1 at the beginning stage. When digital data arrives at the switch 2 and it is equal to the generated clock of the clock generation circuit 3, a register 1 with six steps is filled. Assuming that the pulse generating cycle of the pulse generation circuit 5 is six times the cycle of the circuit 3, a latch pulse is gener ated from the circuit 5 at every arrival and shift of the data of six bits to the register 1, and parallel data transfer is performed from the register 1 to the register 4. Meanwhile, in the register 4, the switch 7 is switched to the terminals a1-a6 by a clock from the clock generation circuit 8, and data shift is performed. Therefore, assuming the frequency of the circuit 6 as the one double that of the circuit 1, it results that the data from the switch 7 is provided with the speed double that of the data inputted to the switch 2.</p> |
