发明名称 |
Phase-locked loop delay line |
摘要 |
A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.
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申请公布号 |
US4922141(A) |
申请公布日期 |
1990.05.01 |
申请号 |
US19880205517 |
申请日期 |
1988.06.03 |
申请人 |
WESTERN DIGITAL CORPORATION |
发明人 |
LOFGREN, KARL M. J.;SHEARER, GERALD W.;OUYANG, KENNETH W. |
分类号 |
H03H9/38;H03K5/00;H03K5/13;H03K5/135;H03L7/081 |
主分类号 |
H03H9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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