发明名称 ERROR CHECKING SYSTEM FOR INTERFACE DEVICE
摘要 PURPOSE:To increase the effective processing speed of a system by counting the continuous number of the times of error generations and when the number of the times of the error generations is a constant value or below, sending the previous data. CONSTITUTION:The output (CRC error presence absence signal 10) of a CRC checking circuit 3 is inputted to a CRC error counter 7 and the counting of the error generation is executed. When the signal 10 outputted from the CRC checking circuit 3 shows that the error generation is present, the counted value of the CRC error counter 7 is a constant value or below and the output is not executed, the previously sent data are outputted to a computer side as the present data. Thus, since the computer executes the processing which is not changed in the same way as the sequence at the normal time, the high speed processing can be carried out.
申请公布号 JPH02116233(A) 申请公布日期 1990.04.27
申请号 JP19880269817 申请日期 1988.10.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAITO SEIICHI
分类号 G06F11/00;G06F13/00;H04L1/00 主分类号 G06F11/00
代理机构 代理人
主权项
地址