| 摘要 |
PURPOSE:To increase the processing speed of a reverse projection of a CT, to develop easily firmware, and also to improve the efficiency and economical property by providing in parallel a part of apparatuses among all devices such as an adder, a multiplier, etc. CONSTITUTION:A multiplier MUL1 and MUL2 execute multiplication between each output of register files RF1, RF2, FR3, and RF4, respectively, and as a result, MO1 and MO2 are given to an input 1 of an adder ADD1 and an input 1 of an ADD1, respectively. Also, an output of a memory MM or an output (AO2) of the ADD2 is provided to an input 2 of the ADD1, and as a result, AO1 is given to an input 2 of the ADD2. The ADD2 gives its result to the input 2 of the ADD1 or a buffer register BF, and the register BF stores an output of the ADD2, reads it out at suitable timing, and gives it to the memory MM. That is to say, write and read on and from different addresses can be executed simultaneously, therefore, the processing speed of a reverse projection is increased, firmware is developed easily, and the efficiency and economical property can be improved. |
