| 摘要 |
PURPOSE:To obtain a delay time with a comparatively large degree of freedom by devising the circuit such that plural delay synchronizing frequency dividers receiving a reference signal and a delay time signal from a source oscillator from a time having a time delay being a multiple of N of the delay time by each source oscillator. CONSTITUTION:When a DATA is loaded, a count output CO terminal of clock synchronizing counters 6, 7, 8 goes to an L level. As a result, since the enable terminal foes to an H level, the count is started. The DATA is incremented by '1' every time a clock signal 2 is inputted from a source oscillator 1 in the count operation. When an input to a clear terminal goes to an H level, the count operation is implemented every time the clock signal 2 is inputted from the source oscillator 1 and plural kinds of frequency division clock signals 7, 8, 9 synchronously with the clock signal 2 of the source oscillator 1 are obtained. Thus, the system has a higher degree of freedom than that of a delay line system and the circuit with a low cost is obtained. |
