| 摘要 |
PURPOSE:To realize the conversion to non-adjustment, also IC, a small size, and also one chip in all digital systems, by inputting an input signal train quantized at a higher speed of two times of a transmission rate, to a phase interpolating circuit and a phase detecting circuit, and controlling said phase interpolating circuit and a clock selecting circuit. CONSTITUTION:A signal train quantized a digital information signal transmitted by F.b.p.s as an input signal, by two times of a transmission rate is inputted to a phase interpolating circuit 8 and a phase detecting circuit 10. The phase detecting circuit 10 detects phase information from the input signal and outputs it to a control circuit 9. The control circuit controls a selecting circuit 11 and outputs a timing clock to a signal decoding circuit 12. The phase interpolating circuit 8 receives a control signal from the control circuit 9, executes an optimum interpolation, outputs it to a signal decoding circuit 11, and it is decoded. |
