| 摘要 |
PURPOSE:To reduce a chip area by installing the following: a firstlayer wiring part of a first passage channel between two gates inside a fundamental cell; a first-layer wiring part of a second passage channel between fundamental cells of a fundamental cell row; a second-layer wiring part of a third passage channel which is piled up on the first-layer wiring part of the second passage channel. CONSTITUTION:The following are installed: a first-layer wiring part 36 as a first passage channel which is extended in an X direction between two gates inside fundamental cells 3; a firstlayer wiring part 47 as a second passage channel which is extended in the X direction between the fundamental cells 30 of a fundamental cell row. In addition, second-layer wiring parts 40 to 50 as a third passage channel which are extended in the X direction are installed intermittently and by being piled up by a first-layer wiring part 47 as the second passage channel in such a way that they do not come into contact with second-layer wiring parts 42, 44 for electric wire use which are extended in a Y direction. Accordingly, it is sufficient to keep a space which can lead one wiring part between the fundamental cells 30 of the fundamental cell row; an integration density is enhanced as compared with a conventional circuit. Thereby, a chip area is reduced. |
