| 摘要 |
<p>A technique for transferring byte-wide serial data from a UART to a word-wide parallel data bus and vice versa is provided. Input control signals are established for the UART to specify the type of transfer to be implemented: odd byte, even byte or word. When a single byte is being sent from a CPU to a UART FIFO for serial transmission, then the predetermined storage location within the UART depends upon the address and the number of bytes being sent, not upon the byte's position on the data bus as is conventional. Similarly, when a serially received byte is to be transferred from a UART FIFO to the CPU, the next byte available is transferred to the data bus regardless of the position on the bus that it will occupy; in other words, regardless of whether it will be in the high byte or low byte position.</p> |
