| 摘要 |
<p>An interface arrangement is provided for interfacing, for example, a host computer with a tape drive. The interface arrangement includes a buffer memory (20), a first input/output channel (10,17) connecting the host computer to the buffer memory (20), and a second input/output channel (13,18) connecting the tape drive to the buffer memory (20). Test circuitry (40) is provided as part of the interface arrangement. The test circuitry (40) is operable to generate a test pattern to be down-loaded to the tape drive and then read back and compared with the original pattern to verify the operation of the tape drive. Preferably, the test circuitry (40) writes and reads the test patterns to and from the buffer memory (20) so that the transfer of the test patterns between the interface arrangement and the tape drive can be effected using the same procedures as for normal data transfers. The test circuitry (40) can also be used to check the buffer memory (20).</p> |
