Semiconductor memory device with memory cells including ferroelectric capacitors.

摘要

A semiconductor memory device includes bit line pairs including first and second bit lines (BL, BL) to be set at a first logic level or a second logic level, and a first memory cell (MC1) coupled with the first bit line (BL) of the bit line pairs. The first memory cell contains a first ferroelectric capacitor (C1) with first and second electrode plates, and a first transistor (T1) coupled between the first electrode plate of the first ferroelectric capacitor (C1) and the first bit line (BL). A potential at the second electrode plate of the first ferroelectric capacitor (C1) is set at a mid value between the first and second logic levels. A distance D (cm) between the first and second electrode plates of the first ferroelectric capacitor (C1) being selected such that a minimum voltage Et x D to saturate the intensity of polarization of the first ferroelectric capacitor (C1) is smaller than the value amounting to substantially half of the difference between the first and second logic levels, where Et indicates a field strength enough to the intensity of the saturate polarization of the first ferroelectric capacitor (C1) and is expressed in V/cm.