| 摘要 |
PURPOSE:To simplify a process, improve reproducibility, and enable cell arrangement of high density by forming lower electrodes of capacitors and electrodes for leading out bit lines, in a recessed part interposed between narrow portions. CONSTITUTION:Narrow portions 1, 2 are formed between a plurality of word lines WL11-W15,which are arranged closely at an arbitrary point part 3 and an arbitrary line part 4. The distance of close arrangement is a distance wherein insulating films coating the word lines WL11-WL15 only are buried in the side wall of the word lines. The lower electrodes 19 of capacitors and electrodes for leading out bit lines are also formed in a recessed part 5 formed in the narrow portions 1, 2. Hence, it becomes possible that a conducting layer is formed in a self-alignment manner in the recessed part 5 interposed between the narrow portion 1, 2. Thereby, a patterning process is simplified, the size of a cell is reduced, and high density integration is enabled. |
