| 摘要 |
<p>PURPOSE:To simplify the constitution and to improve the tracking at the changeover of a clock selection signal, by directly synchronizing an asynchronous clock with a basic clock. CONSTITUTION:Flip-flops F21, F22 and F23 in a synchronizing circuit are normally reset. On the other hand, the leading of an external clock phiE is detected with a delay circuit 11, an inverter 12 and an AND gate 13 and the F21 is set. When an internal clock phi1 is ''0'', that is, when the clock is ''1'' at an inverter 14, after the F21 is set, the output of the F21 is fetched and set at the F22 of the next stage. The F23 latches the content of the F22 when the phi1 is ''0'' and a phi2 is ''1''. The F22 and F23 are to be fetched when the clocks are ''1'' at phi1=''0'' and phi2=''1'', and when the phiE is changed at this time, the F21-F23 are conductive and the change in the phiE is directly transmitted. When the F23 is set, the F22 is reset at phi2=''1'' at the latter half the phiE=''1'' afterward.</p> |
