| 摘要 |
<p>PURPOSE:To improve the followup ability of a clamping circuit by controlling the clamping potential of an analog clamper by the output signal of an adder. CONSTITUTION:While the first register 6 operates so as to extract a sampled value in a horizontal synchronizing signal period in an A/D-converted MUSE signal every one hour, the second register 7 operates so as to delay the output of the first register for one hour. Since an adder 8 adds the respective outputs of the first and second registers, the sampled values of a horizontal synchronizing signal can be added between lines. Consequently, the fluctuation of the reference level of clamping can be detected by executing comparison in order to decide whether a value to be obtained for the output of the adder 8 is quantized to another value specified at a transmitting side or not. Thus, since a cycle for detecting the reference level of the clamping can be set from a field cycle to a horizontal cycle, a feedback clamping circuit can be made into the one having a wide band, and the followup ability for the fluctuation of the reference level of the clamping can be improved.</p> |
