发明名称 CLAMP AMPLIFYING CIRCUIT
摘要 PURPOSE:To realize a clamp amplifying circuit so that an A/D converter can automatically go to a maximum dynamic range to respective signals in correspondence to the type of an input signal by providing a horizontal synchronization detecting circuit, a vertical synchronization detecting circuit and an AND circuit. CONSTITUTION:The input signal from an input terminal 11 is simultaneously inputted to a horizontal synchronization detecting circuit 12 and a vertical synchronization detecting circuit 13 and when the input signal is a picture signal, horizontal synchronization and vertical synchronization are detected. Then, a clamp amplifying circuit 15 is caused to be in a clamp 'turning-on' state by the output of the AND circuit 14. As a result, for the picture signal, for example, the tip of the synchronization is clamped by a rated voltage and inputted to an A/D converter circuit 16. Thus, the A/D converter 16 presents the maximum dynamic range. On the other hand, when the input signal is not the picture signal but a sine-wave signal, the clamp amplifying circuit 15 is caused to be in a clamp 'turning-off' state by the output of the AND circuit 14. Then, even in such a case, the dynamic range is made maximum by the set of output off-set.
申请公布号 JPH02112386(A) 申请公布日期 1990.04.25
申请号 JP19880264785 申请日期 1988.10.20
申请人 NEC CORP;NEC MIYAGI LTD 发明人 TAKEMATA MICHIYUKI;ITABASHI SHUNICHI
分类号 H04N5/18;H03K5/00;H03K5/007 主分类号 H04N5/18
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