| 摘要 |
PURPOSE:To make the operation of gate stable by inputting logic signals including a timing where logic is not inverted and being other signals than the inverted logic signals to gates comprising p-channel and n-channel transistors(TRs). CONSTITUTION:Logic signals phi1, phi2 are supplied even to a clocked gate inverter 1b of a 2nd stage in the case of applying the circuit to a shift register circuit and the logic signals phi1, phi2 of the opposite polarity to above are supplied to a clocked inverter 1c of a 3rd stage. Then the timing as to the logic signals phi1, phi2, that is, a time difference DELTAt is selected to nearly a time DELTAT where the pulse is unsharpened. For example, in the case of a clock signal in 1MHz, the time DELTAT is selected to be 60nsec. Thus, the overlap of the transition time of the ON/OFF of the two logic signals phi1, phi2 is almost eliminated. Then a shift register circuit operated more stably is attained. |
