| 摘要 |
PURPOSE:To increase the utility of a gate cell to a chip by constructing a semiconductor integrated circuit with, a region where a gate cell array and a wiring channel are formed, and a region over which the gate cell is laid. CONSTITUTION:A master chip portion 11 comprises a fixed channel region 12 and a free channel region 13. On the fixed channel region 12, many gate cells 14 corresponding to a basic transistor circuit are disposed into an array. Wiring channels 15 are disposed between the gate cells. On the free channel region 13, the gate cells 14 are laid over the entire surface thereof. Such a master chip is previously manufactured in a master process. In response to a user's request, in the fixed channel region 12, longitudinal and transversal wiring layers are formed in the wiring channel 15 to interconnect the gate cells 14. Further, in the free channel region 13, wiring is freely laid on the gate cells 14 to make available the fixed channel region 12 and the free channel region 13 as a logic circuit and a memory. Hereby, the utility of the fixed and free channel regions can be raised. |
