发明名称 |
Digital video signal encoding arrangement, and corresponding decoding arrangement |
摘要 |
A digital video signal encoding arrangement comprising a correlation reducing circuit receiving said digital signals which are representative of the luminance or the chrominance of a certain number of elements of a picture which has been divided into blocks, a scanning conversion circuit (30), a normalization circuit (50), a quantizing circuit (60), a circuit (70) for encoding said quantized values and a rate controlling circuit (80). This arrangement is characterized in that its normalization circuit itself comprises: (a) a weighting coefficient storage memory (51) which is addressed on the one hand by an index i indicating the position in the current block, and on the other hand by a value representative of the activity of this block; (b) a standard calculating circuit (52) on the basis of a mean standard value produced by the rate controlling circuit and also on the weighting coefficient supplied; (c) a circuit (59) for dividing by the coefficient Ki the output of said standard calculating circuit.
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申请公布号 |
US4920414(A) |
申请公布日期 |
1990.04.24 |
申请号 |
US19880250019 |
申请日期 |
1988.09.27 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
REMUS, CHRISTIAN;CHANTELOU, OLIVIER |
分类号 |
H04N11/04;H04N1/41;H04N7/26;H04N7/30 |
主分类号 |
H04N11/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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