发明名称 BUFFER MEMORY CIRCUIT FOR PACKET TRANSMISSION
摘要 <p>PURPOSE:To attain proper processing to a faulty state by detecting positively the occurrence of overflow and underflow state and selecting a packet address for write and read processing through the use of the result. CONSTITUTION:An overflow detection means 101 detects the occurrence of an overflow state from packet address information from a write address advancing means 81 and packet address information of a readout address storage area 72. An overflow detection means 102 detects the occurrence of an underflow state from packet address information from a write address advancing means 91 and packet address information of a readout address storage area 71. A write address selection means 820 in the detection of the overflow state selects a packet address obtained by a remotest write address designation means 82 as a packet address for write processing. A readout address selection means 90 in the detection of the underflow state selects a packet address obtained by a remotest readout address designation means 92 as a packet address for the readout processing.</p>
申请公布号 JPH02111137(A) 申请公布日期 1990.04.24
申请号 JP19880264454 申请日期 1988.10.20
申请人 FUJITSU LTD 发明人 MATSUDA TAKAO
分类号 H04L12/56 主分类号 H04L12/56
代理机构 代理人
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