| 摘要 |
PURPOSE:To obtain a semiconductor memory provided with an electrically erasable EEPROM cell which is small in size, capable of being highly integrated, and possessed of a gate electrode of a three-layered structure by a method wherein a source region and a drain region of cell transistors adjacent to each other in a lengthwise direction of a channel are formed in common with each other and other processes are performed. CONSTITUTION:In a nonvolatile semiconductor memory provided with a cell array composed of EEPROM cells which are arranged in a matrix and provided with gate electrodes 8, 9, and 5 of a three-layered structure, a floating gate transistor forming a channel region through the floating gate electrode 8, and a control gate transistor forming a channel region through the control gate electrode 5, a source region 3 and a drain region 4 of the memory cell are provided in parallel with each other, the source region 3 and the drain region 4 of the adjacent cells in a channel lengthwise direction of a channel region are formed in common, and the erasure gate electrode 9 and the control gate electrode 5 are provided in parallel with each other along a direction perpendicular to a broadwise direction of a channel region between the source region 3 and the drain region 4. |
