RAM SHARING CIRCUIT FOR DATA INTER-TRANSMISSION

摘要

The circuit for sharing a memory region by two CPU in a multiprocessor system includes a control circuit comprising decoders (21,22), a JK flipflop (23), and OR gates (OR1-4). The flipflop performs a logical operation to provide buffer enable signals (CS1-2) corresponding to the access signal of the two CPU. The OR gates performs the operation to be accessed only by one signal of the two signals of the CPUs and to send a wait signal to the other CPU so that the bus crash of two CPUs is prevented.