THE COMPLEMENTARY SEMICONDUCTOR MEMORY DEVICE

摘要

The complementary semiconductor memory device comprises a memory cell array, each cell having a MIS transistor of a conduction type constituting an access or transfer gate, connected to a respective one of a number of word lines. A circuit decodes an address signal input and a selecting signal is based on the result of the decoding. A driving circuit has a second MIS transistor of a second conduction type opposite to the first conduction type for selecting a specific word line among the number of word lines in response to the selecting signal.