| 摘要 |
The dynamic semiconductor memory device has a matrix arrangement of memory cells each designated by a row address, a column address, an error checking and correcting circuit. The row address is received from an exterior in response to a row address strobe signal and the column address is received from the exterior in response to a column address strobe signal. A refresh operation is performed when the column address strobe signal becomes low before the low address strobe signal. Refresh operations are selectively performed with and without an error checking and correcting operation depending on timings of the row and column address strobe signals. |
