| 摘要 |
<p>A data bus processing system having a host processor (10) interfaced with a GBUS controller (12) which arranges for rapid data transfer from a host memory (14) to the memories of any one of a number of devices (24, 26) on the GBUS (16) and wherein, to speed up operation, each device (24, 26) has a buffer memory with direct memory access in parallel with the GBUS, one of said devices includes a system controller (28) controlled by the processor (10) and, in each device on the GBUS, the function control input of the processor (10) is instructed by the system controller (28).</p> |
