| 摘要 |
PURPOSE:To detect that clock signals of different phases are simultaneously set to active levels in a short time by respectively adding malfunction detection circuits to final ends of each clock line. CONSTITUTION:In a malfunction detection circuit section 102, an AND/NOR gate G22 and NOR gate G23 constitute a flip flop. The NOR gate G23 is set to a low level by means of a reset signal S18 which initializes a CPU. Then, when the active level of clock signals S12 and S13 is inputted to the AND/NOR circuit G22, the AND gate of the gate G22 generates an AND signal and the gate becomes high in level. Therefore, when the output signal S19 of the NOR gate G23 which becomes the high level is read out to the outside through a detecting terminal D, it can be recognized that both clock signals S12 and S13 simultaneously set to active levels. |
