发明名称 Automated error detection for multiple block memory array chip and correction thereof
摘要 A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.
申请公布号 US4918692(A) 申请公布日期 1990.04.17
申请号 US19880201413 申请日期 1988.06.02
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 HIDAKA, HIDETO;FUJISHIMA, KAZUYASU;MATSUDA, YOSHIO
分类号 G11C29/00;G06F11/10;G11C11/401;G11C29/04;G11C29/42;H01L27/10 主分类号 G11C29/00
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