| 摘要 |
PURPOSE:To stably hold data even in a long data holding cycle by adding a multiplexer to a dynamic latch. CONSTITUTION:In each of memory cells 1 - 4, the clocked inverters 12 and 13 are successively connected to a 2-input multiplexer 11 which uses the external input as the 1st input and driven by the clocks phi1 and phi2 respectively. Then the output Q of the inverter 13 is acquired at a terminal 10 and supplied to the 2nd input of the multiplexer 11. Both inverters 12 and 13 form a dynamic latch, and the multiplexer 11 selects the data on the J0 side when a shift control signal 6 supplied from a terminal 6 is kept at 'L' and then selects the data on the J1 side when the signal 6 is kept at 'H' to output these data to the dynamic latches 12 and 13. In other words, the multiplexer 11 fetches the external data in a period I and otherwise circulates its own data to stabilize a dynamic holding state. Then the multiplexer 11 outputs the data to the cell of the next stage in the second period I and fetches the output of the preceding stage. In such a constitution, the data can be held stably even in a long data holding cycle. |
