Semiconductor memory device with P-channel MOS transistor load circuit

摘要

A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.