| 摘要 |
<p>PURPOSE:To process a sequential input and output instruction and to cope with the increase in the number of issues of instructions, by preventing old instruction out of input and output instructions from being annihilated, through the DMA transfer of input and output instruction information and output data information to a memory in an input and output control mechanism in the order of issue. CONSTITUTION:An input and output controlling mechanism 6 is connected to an input and output interface bus 2 connected to a processor 1, and input instruction information register 9, output data information register 10, memory 11, microprocessor 8, and input and output control circuit 15 are connected to a common bus 7 of the mechanism 6. Further, a DMA controlling section 18 is connected among registers 9, 10, a storage pointer register 12, memory 11 and processor 8. The memory 11 is provided with an input and output instruction information storage area 22 and an output data information storage area 23, an instruction transfer discriminating circuit 17 discriminates the information received with the area 22 and data transferred to the area 23, and the instruction information and the output data are transfered to the memory 11 in the order of issue. The input information is sequentially processed to prevent old instructions from being lost.</p> |
