| 摘要 |
<p>PURPOSE:To prevent the increase in transmission delay resulting from unprocessed cells with low priority by storing the cells with low priority to an input buffer means if a cell with high priority is invalid due to same destination. CONSTITUTION:Input buffers #0-#n are connected respectively to input terminals #0-#n to input a cell. The input buffers #0-#n are connected to a destination identification circuit 2 via signal lines 2#0-#n and to an exchange circuit 3 via signal lines 3#0-#n respectively. A header of a cell includes a destination display bit representing the destination of the cell and the 3 stages of priority display bit representing the priority of the cell. When the input buffer sends a cell header to a destination information means and the cell header sent by the destination identification means is discriminated to be invalid, the input buffer sends a cell header with lower priority than the invalid cell header to the destination identification means. Thus, the increase in the transmission delay of the cell with low priority is prevented.</p> |
