发明名称 |
Inverter circuit |
摘要 |
An inverter circuit (I3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (VDD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (TE). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.
|
申请公布号 |
US4916385(A) |
申请公布日期 |
1990.04.10 |
申请号 |
US19880262302 |
申请日期 |
1988.10.25 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
TOMIOKA, ICHIRO;UEDA, MASAHIRO;ARAKAWA, TAKAHIKO;HANIBUCHI, TOSHIAKI;OKUNO, YOSHIHIRO |
分类号 |
G01R19/165;G01R31/316;G01R31/317;G01R31/319;H03K17/00;H03K17/16;H03K19/003;H03K19/0948 |
主分类号 |
G01R19/165 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|