| 摘要 |
PURPOSE:To improve the reliability of a wiring with the scaling down and miniaturization of cell size by forming capacitance, shaping a single crystal semiconductor thin-film to the upper section of the capacitane and forming a selective transistor to the single crystal semiconductor thin-film. CONSTITUTION:A single crystal semiconductor thin-film 2 is isolated by dielectrics 4 and active regions are formed, transistors are shaped in each active region, and first conductor layers 18 for capacitance isolated at every active region through dielectric layers 16 are formed to the lower sections of each active region. A second conductor layer 22 for capacitance is shaped to the lower sections of the first conductor layers 18 through a dielectric layer 20 for capacitance and capacitance at every active region is formed, contact holes are shaped in the isolation regions of the single crystal semiconductor thin-film 2, and the selective transistors of the active regions and capacitance 20 under the active regions are connected through the contact holes. Accordingly, the capacitance 20 is formed to the lower sections of the active regions, to which the selective transistors are shaped, thus scaling down the size of a DRAM memory cell, then making a metallic wiring finer than the capacitance 20 is laminated to the upper sections of the active regions. |
