| 摘要 |
PURPOSE:To restrict an increase of a chip area to the minimum and an increase of signal propagation delay time as well as reduce shipping inspection cost by forming an output status control signal wiring into a ring configuration in an input/output circuit region. CONSTITUTION:A test circuit, which is to switch an input signal C, IN into an output buffer typically in an operating state and an input signal TC, TIN into the output buffer in a testing state, is constructed with a control signal switching test circuit 3 and an input signal switching test circuit 4 each comprising a pair of transfer gates, the pair comprising a P channel MOS transistor and an N channel MOS transistor. Further, these test circuits 3, 4 are formed in an output buffer cell region 1 together with the output buffer 2, and testing signal wirings TC, TIN, TEST, NTEST are fixed into a ring shape in the input/output circuit region. Hereby, there is restricted to the minimum an increase of a chip data due to the addition of the test circuits and an increase of signal propagation delay time to reduce shipping inspection cost. |
