Adder circuit in 51111 code

摘要

The adder circuit according to the subject of the invention also processes the value 5 using a dual full adder (4), and the value 1 using a square adder circuit (1), and cannot process a possible carry simultaneously. The maximum one's sum (8) is processed using circuit (3) and OR circuit (43). The size of the main circuit (1) was thus reduced to 15 AND circuits each with two inputs, and 12 OR circuits each with two inputs. In the adder circuit type B1, the size of the main circuit (1b) was further reduced by arranging a one-upwards shift circuit (5). <IMAGE>