发明名称 OUT OF LOCKING PREVENTING CIRCUIT FOR PLL CIRCUIT
摘要 PURPOSE:To prevent occurrence of out of locking in the occurrence of a phase jump of an input clock by detecting the phase jump of the input clock so as to set a frequency division circuit for feedback specifically. CONSTITUTION:A phase jump detection circuit 4 monitors a phase difference between an input clock 5 and a feedback clock 7, outputs a set signal 8 to a frequency divider circuit 3 for feedback of a PLL circuit 2 if any phase jump takes place in the clock 5. Then the circuit 3 is set so that the phase of the clock 7 is in matching with the phase of the clock 5 and the occurrence of out of locking in the PLL circuit 2 in the occurrence of a phase jump in the input clock is prevented.
申请公布号 JPH0294726(A) 申请公布日期 1990.04.05
申请号 JP19880244008 申请日期 1988.09.30
申请人 HITACHI LTD 发明人 MOCHINAGA TATSUO
分类号 H03L7/199;H04L7/08 主分类号 H03L7/199
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