| 摘要 |
<p>A PWM type D/A converter having a first PWM converter (1), a second PWM converter (2) and an analogue adder(5)/subtracter(6). The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered reference timing points are designated as odd/even numbered reference timing points. The first PWM converter receives the digital input signal to output signal whose rising/falling timing point is set at the earlier/later the timing, the larger the value of the odd/even numbered reference timing point relative to the odd numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal. The second PWM converter receives the digital input signal to output signal whose falling/rising timing point is set at the later/earlier the timing, the larger the value of the odd/even numbered reference timing point relative to the odd numbered reference timing point and the pulse width is determined by the values of the even numbered input signal and the next odd numbered input signal. The second PWM converter is also made to determine the output signal by the complementary values of odd numbered input signal and the next even numbered input signal.</p> |
