| 摘要 |
PURPOSE:To permit competition between the write timing and read timing of receiving data or arithmetic processing data by using a FIFO (First In First Out) register for an input buffer and asynchronously executing shift input control timing and shift output timing. CONSTITUTION:A receiving data processing circuit is composed of an input register 21, a FIFO register 22, a CPU interface 23, a timing control circuit 24 and a CPU25. The FIFO register 22 is used for the tentative holding means of the processing data and the shift input control timing and shift output timing of this FIFO register 22 is asynchronously executed. Thus, without executing address control, the competition between both timings can be permitted by the small number of status signals. |
