发明名称 OPERATION PROCESSOR
摘要 PURPOSE:To use a hardware which is used for addition and subtraction processing as well and to execute logical shift and arithmetical shift processing by adding logical function to right and left shifters and providing a bit shifter. CONSTITUTION:A bit shifter 90 is provided in an addition and subtraction executing stage to be composed of a preshifter 30 as the right shifter for digit matching and a post-shifter 110, etc., as the left shifter for normalization. The shifter 90 can execute the shift of (n-1)-bit and remove the code bit of a number to be shifted from a shift object at the time of arithmetical shift. Then, the shifter 90 can shift in the value of the code bit to the number to be shifted only by a shift number at the time of arithmetical right shift. The logic is added to the shifter 30 so that the code bit of the number to be shifted can be removed from the shift object at the time of the arithmetic shift and the value of the code bit can be shifted in the shift number. Then, the logic is added to the shifter 110 so that the code bit of the shift number can be removed from the shift object. Thus, the hardware is used as well and the logical shift and arithmetic shift processing can be executed.
申请公布号 JPH0293728(A) 申请公布日期 1990.04.04
申请号 JP19880244172 申请日期 1988.09.30
申请人 HITACHI LTD;HITACHI COMPUT ENG CORP LTD 发明人 OSADA YUJI;NAKANO HIROSHI
分类号 G06F5/01;G06F7/00;G06F7/76 主分类号 G06F5/01
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