| 摘要 |
<p>PURPOSE:To synchronize the phases of respective systems even when the frequency of a clock rises by detecting a reset signal by the clock and after that, prohibiting the clock for a set period. CONSTITUTION:A first flip-flop 11 is provided to detect a reset signal SCLR to be inputted by a clock OSC, which is inputted from an oscillator, and a second flip-flop 12 and a gate circuit G1 are provided to prohibit a clock output CLK for a set period after the detection. A third flip-flop 13 and a gate circuit G2 are provided to send the detected reset signal to the single or plural systems during the prohibition of the clock CLK and to permit again the clock output later. When a reset output SRESET is changed, the clock output CLK is temporarily prohibited and a level condition is kept. Thus, even when the clock frequency rises, the set-up time and hold time of the reset output SRESET to the clock output CLK are guaranteed and the phases of the operation condition of the respective systems can be synchronized regardless of the element velocity of an output circuit.</p> |
