| 摘要 |
<p>A multiple processor system which uses at least two processors (10, 11), cache memory units (12, 13) associated with the processors respectively, a main memory (20), a plurality of cache buses (16, 17), each of which is connected to all of the cache memory units (12, 13), and a plurality of memory buses (18, 19) connected to the main memory (20). Control units (14, 15) control the use of the cache buses (16, 17) and main memory buses (18, 19) so as to permit simultaneous broadcasting of data and simultaneous transfer of such broadcast data among cache memory units (12, 13) and between cache memory units and the main memory (20) on different ones of the cache buses (16, 17) and the main memory buses (18, 19). The control units (14, 15) further control the buses (16-19) so that data which has been modified by a processor (10 or 11) and stored in its associated cache memory (12 or 13) can be simultaneously transferred both to another cache memory unit (13 or 12) which has requested it and to the main memory (20).</p> |
