Pull up circuit for sense lines in a semiconductor memory

摘要

A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of VCC-VT (where VT is a threshold voltage of a transistor).