发明名称 |
PARITY DETECTION SYSTEM FOR WIDE BUS CIRCUITRY |
摘要 |
<p>A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.</p> |
申请公布号 |
CA1267460(A) |
申请公布日期 |
1990.04.03 |
申请号 |
CA19870533374 |
申请日期 |
1987.03.30 |
申请人 |
UNISYS CORPORATION |
发明人 |
KIM, DONGSUNG R.;KRONIES, REINHARD K. |
分类号 |
G06F11/10;G06F13/00;(IPC1-7):G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|