| 摘要 |
<p>PURPOSE:To reduce the readout period by providing double data sensing systems respectively provided with data lines and sense amplifiers to one memory cell and accessing the memory cell at different timing. CONSTITUTION:During a period T1 of clock pulses, the 1st data sensing system constituted of a data line 4, transistors 5 and 7, and data line capacity 8 performs readout and the 2nd data sensing system constituted of a data line 9, transistors 10 and 12, and data line capacity 13 performs precharge. During another period T2, the switch transistors 7 and 12 for switching are respectively turned off and turned on and the 1st and 2nd data sensing systems respectively perform precharge and readout. In addition, line capacities 8 and 13 having the same capacity as memory cells have are respectively added to the data lines 4 and 9. Therefore, precharge and readout can be performed simultaneously and the readout period can be reduced.</p> |
