发明名称 DELAY LOCK LOOP CIRCUIT IN DIFFUSED SPECTRUM RECEIVER
摘要 <p>PURPOSE: To improve a response speed and the reliability and to extend a detection range by using an inverse spread device that spreads and demodulates a received signal to keep synchronization between a pseudo signal (PN) code generated by a PN code generator and a PN code of the received signal. CONSTITUTION: When a PN code pattern generated from a PN code generator 213 is synchronous with a PN code pattern of a transmission signal, a difference between both patterns is zero. When not, some voltage is outputted from a subtractor 207, and fed to an active low-pass filter of a next stage consisting of an amplifier 211 and a capacitor 210 or the like. A cut-off frequency of the active low-pass filter is selected to decide a response speed of a feedback loop in a delayed lock loop(DLL) circuit. The feedback loop acts like keeping the synchronization state. Since the synchronization of the PN code is attained by using a voltage at a control terminal of a VCO at a high speed with reliability, the synchronization of PN codes at a high speed is realized.</p>
申请公布号 JPH0292035(A) 申请公布日期 1990.03.30
申请号 JP19890145500 申请日期 1989.06.09
申请人 KENWOOD CORP;FUSE NETSUTOWAAKU SYST INC 发明人 NAMIOKA HIROTAKA;HITSUPU BAN FUAN
分类号 H03L7/06;H04B1/707;H04B1/7085;H04L7/00 主分类号 H03L7/06
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